2009   Harvard University, Ph.D 
2004   State University of New York at Stony Brook, MS
2000   Fudan University, B.Eng

2012-present   Shanghai Jiao Tong University, Professor

MS108, Computer System 1
CS427, Multicore Architecture and Parallel Computing

Journal Publications:
? Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, “MicroFix: Using Timing Interpolation and Delay Sensors for Power Reduction,” ACM Transactions on Design Automation of Electronic Systems (TODAES), March 2011. 
? Xiaoyao Liang, Gu-Yeon Wei and David Brooks, “ReVIVaL, Variation Tolerant Architecture Using Voltage Interpolation and Variable Latency,” IEEE Micro Top Picks, January 2009.
? Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David Brooks, “Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability,” IEEE Micro Top Picks, January 2008.


Conference Publications:
? Naifeng Jing, Haopeng Liu, Yao Lu, Xiaoyao Liang, “Compiler Assisted Dynamic Register File in GPGPU,” International Symposium on Low Power Electronics and Design (ISLPED-13), August 2013.
? Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang, “An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU”,  International Symposium on Computer Architecture (ISCA-40), June 2013.
? Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao liang, “AgileRegulator: A Hybrid Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture”, International Symposium on High Performance Computer Architecture (HPCA-18), February 2012.
? GuihaiYan, Xiaoyao Liang, Yinhe Han, Xiaowei Li, “Leveraging the Core-Level Driven Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors,” International Symposium on Computer Architecture (ISCA-37), June 2010.
? Kristen Lovin, Benjamin Lee, Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “Empirical Performance Models for 3T1D Memories,” International Conference on Computer Design (ICCD-09), October 2009.
? Xiaoyao Liang, Benjamin Lee, David Brooks, Gu-Yeon Wei, “Design and Test Strategies for Microarchitectural Post-Fabrication Tuning,” International Conference on Computer Design (ICCD-09), October 2009.
? Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, “MicroFix: Exploiting  Path-Grained Timing Adaptability for Improving Power-Performance Efficiency,” International Symposium on Low Power Electronics and Design (ISLPED-09), August 2009.
? Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “DRAM-based On-Chip Cache Architectures to Combat Process Variations,” Intel 2008 European Research and Innovation Conference, September 2008.
? Gu-Yeon Wei, David Brooks, A. Durlov Khan, Xiaoyao Liang, “Instruction-Driven Clock Scheduling with Glitch Mitigation,” International Symposium on Low Power Electronics and Design (ISLPED-08), August 2008.
? Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “ReVIVaL: A Variation Tolerant Architecture Using Voltage Interpolation and Variable Latency,” International Symposium on Computer Architecture (ISCA-35), June 2008.
? Xiaoyao Liang, Gu-Yeon Wei, David Brooks, “A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency,” IEEE International Solid State Circuit Conference (ISSCC-08), February 2008.
? Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “Process Variation Tolerant 3T1D-based Cache Architectures,” 40th International Symposium on Microarchitecture (MICRO-40), December 2007.
? Xiaoyao Liang, Kerem Turgay, David Brooks, “Architectural Power Models for SRAM and CAM Structures Based on Hybrid Analytical/Empirical Techniques,” International Conference on Computer Aided Design (ICCAD-07), November 2007.
? Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, “Process Variation Tolerant Register Files Based on Dynamic Memories,” Workshop on Architectural Support for Gigascale Integration (ASGI-07), in conjunction with ISCA 2007, June 2007.
? Xiaoyao Liang and David Brooks, “Mitigating the Impact of Process Variations on CPU Register File and Execution Units,” 39th International Symposium on Microarchitecture (MICRO-39), December 2006.
? Xiaoyao Liang and David Brooks, “Microarchitecture Parameter Selection to Optimize System Performance under Process Variation,” International Conference on Computer Aided Design (ICCAD-06), November 2006.
? Mark Hempstead, Xiaoyao Liang, Patrick Mauro, Gu-Yeon Wei, David Brooks, “Design and Implementation of An Ultra Low Power System Architecture for Wireless Sensor Network Applications,” SRC Techcon, SoC Design Contest - Phase II, 1st place, October 2006.
? Xiaoyao Liang and David Brooks, “Latency Adaptation for Multi-ported Register Files to Mitigate the Impact of Process Variations,” Workshop on Architectural Support for Gigascale Integration (ASGI-06), in conjunction with ISCA 2006, June 2006.
? Xiaoyao Liang and David Brooks, “Highly Accurate Power Modeling Method for SRAM Structures with Simple Circuit Simulation,” The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (p=ac2), September 2005.
? Xiaoyao Liang, Akshay Athalye, Sangjing Hong, “Equalizing Execution Path for Processing Speed Determination in Block Level Pipelining,” IEEE International Symposium on Circuits and Systems (ISCAS-05), May 2005.
? Xiaoyao Liang, Akshay Athalye, Sangjing Hong, “Dynamic Corse Grain Dataflow Reconfiguration Technique for Real-Time System Design,” IEEE International Symposium on Circuits and Systems (ISCAS-05), May 2005.
? Mark Hempstead, Xiaoyao Liang, Patrick Mauro, Gu-Yeon Wei, David Brooks, “Design and Implementation of An Ultra Low Power System Architecture for Wireless Sensor Network Applications,” SRC Techcon, SoC Design Contest - Phase I, 2nd place, October 2005.
? Yulei Weng, Sankalp Kallakuri, Xiaoyao Liang, Alex Doboli, et. al, “Dynamic Architecture Adaptation to Improve Scalability of Sensor Networks: A Case Study for a Smart Sensor for Face Recognition,” 25th IEEE International Real-Time Systems Symposium(RTSS-04), December, 2004.
? Sangjin Hong, Xiaoyao Liang, Petar Djuric, “Reconfigurable Particle Filter Design Using Dataflow Structure Translation”, IEEE Workshop on Signal Processing Systems (SIPS-04), September 2004.
? Sangjin Hong, Xiaoyao Liang, Miodrag Bolic, Petar Djuric, “Data Centric SIR Particle Filter Design Using Buffer-level Pipelining”, 7th International Conference on Signal Processing (ICSP-04), August 2004.
? Sangjin Hong, Xiaoyao Liang, Miodrag Bolic, Petar Djuric, “Design and Synchronization of Gaussian Particle Filter Using Distributed Controller Scheme”, 7th International Conference on Signal Processing (ICSP-04), August 2004.
? Sangjin Hong, Magesh Sadasivam, Xiaoyao Liang, “Post-Generation of Overall Execution Controller for Data Centric Signal Processing Algorithms,” 7th International Conference on Signal Processing (ICSP-04), August 2004. 
 
Awards 
? Awarded CCF-Intel Young Faculty/Researcher Honor Program 2013
? Won 1st Prize of SJTU All English Teaching Competition 2013
? Selected into “1000 People Plan (Young Talent)” by Chinese central government 2012 
? Two papers selected into IEEE Micro’s “Top Picks in Computer Architecture” special issues. “Top Picks” is awarded to 10 most outstanding and industry relevant papers from all top architecture conferences annually 2008, 2009
? One paper was nominated for best paper award at ISLPED 2008
? One paper was nominated for CACM special issue by SIGMICRO 2007
? Won 1st prize of SRC SoC IC Design Challenge, awarded to the champion of 38 teams from top American universities 2005-2006