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Modern Hardware Margins: CPUs, GPUs, FPGAs

Dimitris Gizopoulos, Vijay Janapa Reddi, Behzad Salami, George Papadimitriou, Athanasios Chatzidimitriou, Osman S. Unsal, Adrian Cristal Kestelman, Jingwen Leng

In Proc. of IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019

Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of the most efficient methods to reduce power consumption of a chip. With the galloping adoption of hardware accelerators (i.e., GPUs and FPGAs) in large datacenters and other large-scale computing infrastructures, a comprehensive evaluation of the safe voltage reduction levels for each different chip can be employed for efficient reduction of the total power. We present a survey of recent studies in voltage margins reduction at the system level for modern CPUs, GPUs and FPGAs. The pessimistic voltage guardbands inserted by the silicon vendors can be exploited in all devices for significant power savings. Voltage reduction can reach 12% in multicore CPUs, 20% in manycore GPUs and 39% in FPGAs.