Please refer to my google scholar citation:
http://scholar.google.com/citations?hl=en&user=wCxFd8YAAAAJ
Journal Publication:
[TPDS’17] Naifeng Jing, Jianfei Wang, Qinqin Wang, Li Jiang, Chao Li, Xiaoyao Liang, “IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs”, to appear in Transactions on Parallel and Distributed Systems, 2018 (CCF-A)
[TCAD’17] Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo and Xiaoyao Liang, “CNFET-based High Throughput SIMD Architecture”, to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017 (SCI, CCF-A)
[TVLSI’17] Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, Xiaoyao Liang, "Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, pp. 520 _ 533, 2017 (SCI, CCF-B)
[TCAD’16] Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing and Li Jiang*, "A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 7, pp. 1192 - 1205, 2016 (SCI, CCF-A)
[TC’16] N. Jing, L. Jiang, T. Zhang, F. Fan, C. Li and X. Liang, "Energy Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs", IEEE Transactions on Computers, vol. 65, no. 1, pp. 122 - 135, 2016 (SCI, CCF-A)
[TVLSI’15] Xiaolong Zhang, Huiyun Li, Li Jiang, Qiang Xu. "A Low-Cost TSV Test and Diagnosis Scheme Based on Binary Search Method", IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 11, pp. 2639 - 2647, 2015 (SCI, CCF-B)
[TCAD’13] Li Jiang, Qiang Xu and Willian Eklow, "On Effective Through-Silicon Via Repair for 3D-Stacked ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.32, no.4, pp.559 - 571, April, 2013 (SCI, CCF-A)
[TVLSI’11] Li Jiang, Qiang Xu, Krishnendu Chakrabarty and T. M. Mak., "Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, no.9, pp. 1621 - 1633, 2011 (SCI, CCF-B)
Conference Publication:
[FPGA’18]. Haiyue Song, Xiang Song, Tianjian Li, Naifeng Jing, Xiaoyao Liang and Li Jiang*, “A FPGA friendly approximate computing framework with hybrid Neural networks”, accepted by ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018 (Poster) (CCF-B)
[DATE’18]. Houxiang Ji, Linghao Song, Li Jiang, Hai (Halen) Li and Yiran Chen, “RECOM: An Efficient Resistive Accelerator for Compressed Deep Neural Networks”, accepted by ACM/IEEE Design Automation and Test in Europe Conference, 2018 (CCF-B)
[DATE’18]. Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang and Li Jiang*, “In-growth Test for Monolithic 3D SRAM”, accepted by ACM/IEEE Design Automation and Test in Europe Conference, 2018 (CCF-B)
[DAC’17]. Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang and Li Jiang*, “On Quality Trade-off Control for Approximate Computing using Iterative Training”, ACM/IEEE Design Automation Conference, Article 52, 2017 (CCF-B)
[DAC’17]. Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang and Li Jiang*, “Sneak-path based Test and Diagnosis for 1R RRAM Crossbar using Voltage Bias Technique”, ACM/IEEE Design Automation Conference, Article 38, 2017 (CCF-B)
[DATE’17]. Lerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang and Li Jiang*, “Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar”, ACM/IEEE Design Automation & Test in Europe Conference and Exhibition, pp. 19 - 24, April. 2017 (CCF-B)
[DATE’17]. Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee and Li Jiang*, “Fault Clustering Technique for 3D Memory BISR”, ACM/IEEE Design Automation & Test in Europe Conference and Exhibition, pp. 560 - 565, April. 2017 (CCF-B)
[ITC’16]. Tianjian Li, Li Jiang*, Xiaoyao Liang, Qiang Xu and Krishnendu Chakrabarty, “Defect Tolerance for CNFET-based SRAMs”, IEEE International Test Conference, paper 4.1, Nov. 2016 (CCF-B)
[ICCD’16]. Tianjian Li, Li Jiang*, Naifeng Jing, Nam Sung Kim and Xiaoyao Liang, “CNFET-Based High Throughput Register File Architecture”, IEEE International Conference on Computer Design, pp. 662 - 669, Oct. 2016 (CCF-B)
[MICRO’16]. Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li and Xiaoyao Liang, “Cache-Emulated Register File: An Integrated On-Chip Memory Architecture for High Performance GPGPUs”, ACM/IEEE International Symposium on Microarchitecture, pp. 1 - 12, 2016 (CCF-A)
[ICCD’15]. Li Jiang, Xiangwei Huang, Hongfeng Xie, Qiang Xu, Chao Li, Xiaoyao Liang and Huiyun Li, “A Novel TSV Probing Technique with Adhesive Test Interposer”, International Conference on Computer Design, pp. 597 - 604, Oct. 2015 (CCF-B)
[ITC’15]. Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang and Qiang Xu, “On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement”, International Test Conference, paper 17.1, Oct. 2015 (CCF-B)
[ITC’15]. Li Jiang, and Qiang Xu, “Yield and Reliability Enhancement for 3D ICs”, International Test Conference, paper DDC.3, Oct. 2015 (CCF-B)
[NOCS’15]. Li Jiang, and Qiang Xu, “Fault-tolerant 3D-SoCs: Recent advances and challenges”, Network-on-chip Symposium, pp. 1 - 8, Sep. 2015 (CCF-C)
[IEEE-SOCC’15]. Tianjian Li, Hao Chen, Weikang Qian, Xiaoyao Liang, and Li Jiang*, “On Microarchitectural Modeling for CNFET-based Circuits”, IEEE System On Chip Conference, Sep. 2015
[IEEE-SOCC’15]. Chen Wang, Li Jiang*, Tianjian Li, Xiaoyao Liang, Weikang Qian, “Timing-Driven Placement for Carbon Nanotube Circuits”, IEEE System On Chip Conference, Sep. 2015
[ISLPED’15]. Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, Xiaoyao Liang, “Bank Stealing for Conflict Mitigation in GPGPU Register File”, International Symposium on Low Power Electronics and Design, pp. 55 - 60, July 2015 (CCF-B)
[ICS’15]. Yiqing Hua, Chao Li, Weichao Tang, Li Jiang, Xiaoyao Liang, “Building Fuel Powered Supercomputing Data Center at Low Cost”, International Conference on Supercomputing, pp. 241 - 250, June 2015 (CCF-B)
[DAC’15] Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing and Li Jiang*, “Jump Test for Metallic CNTs in CNFET-Based SRAM”, Design Automation Conference, pp. 1 - 6, 2015 (CCF-B)
[ASP-DAC’13] Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang and Xinli Gu, “On Test Syndrome Merging for Reasoning Based Board-Level Functional Fault Diagnosis”, Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 737 - 742, 2013 (CCF-C)
[ITC’13] Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang and Xinli Gu, “AgentDiag: An Agent-Assisted Diagnostic Framework for Board-Level Functional Failures”, IEEE International Test Conference (ITC), paper 11.2, 2013 (CCF-C)
[DAC’13] Li Jiang, Qiang Xu, Feng Ye, Krishnendu Chakrabarty and Bill Eklow, “On Effective and Efficient In-Field TSV Repair for Stacked 3D ICs”, Proc. ACM/IEEE Design Automation Conference, pp. 1 - 6, 2013 (CCF-B)
[DATE’12] Li Jiang, Qiang Xu and Bill Eklow, “On Effective TSV Repair for 3D-Stacked ICs”, Proc. Design, Automation & Test in Europe Conference & Exhibition, pp. 793 - 798, 2012 (CCF-B)
[ASP-DAC’12] Qiang Xu, Li Jiang, Huiyun Li and Bill Eklow, “Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges”, Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 731 - 737, 2012 (Invited) (CCF-C)
[ICCAD’10] Li Jiang, Rong Ye and Qiang Xu, “Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing across Dies”, Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 230 - 234, 2010 (Nominated for Best Paper Award) (CCF-B)
[ITC’10] Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie and Qiang Xu, “Modeling TSV Open Defects in 3D-Stacked DRAM”, Proc. IEEE International Test Conference, pp. 1 - 9, 2010 (CCF-B)
[ICCAD’09] Li Jiang, Qiang Xu, Krishnendu Chakrabarty and T. M. Mak, “Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint”, Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 191 - 196, 2009 (CCF-B)
[DATE’09] Li Jiang, Lin Huang and Qiang Xu, “Test Architecture Design and Optimization for Three-Dimensional SoCs”, Proc. IEEE/ACM Design, Automation, & Test in Europe, pp. 220 - 225, 2009 (CCF-B)